HyperTransport System Architecture

Annotation The MindShare Architecture SeriesThe MindShare Architecture book series currently includes the books listed below. Rather than duplicating common information in each book, the series uses the building-block approach. Generally speaking,ISA System Architectureis the core book upon which the others build. In a sense, it is a PC-compatibility book. The entire book series is published by Addison-Wesley.Books about Processor Architecture:80486 System Architecture, Third Edition, 0-201-40994-1Pentium Processor System Architecture Second Edition, 0-201-40992-5Pentium Pro and Pentium II System Architecture, Second Edition, 0-201-30973-4Power PC System Architecture, 0-201-40990-9Books About Bus Architecture:PCI System Architecture, Fourth Edition, 0-201-30974-2PCI-X System Architecture, 0-201-72682-3EISA System Architecture, 0-201-40995-X--Out-of-printFirewire System Architecture, Second Edition: IEEE 1394a, 0-201-48535-4ISA System Architecture, Third Edition, 0-201-40996-8Universal Serial Bus System Architecture, 0-201-46137-4HyperTransport System Architecture, 0-321-16845-3Books About Network Architecture:Network Architecture Infiniband Network Architecture, 0-321-11765-4Books About Other Architectures:PCMCIA System Architecture, Second Edition: 16-Bit PC Cards, 0-201-40991-7CardBus System Architecture, 0-201-40997-6Plug and Play System Architecture, 0-201-41013-3Protected Mode Software Architecture, 0-201-55447-XAGP System Architecture, 0-201-37964-3Cautionary NoteThe reader should keep in mind that MindShare's book series often details rapidly evolving technologies. That being the case, it should be recognized that the book is a "snapshot" of the state of the technology at the time the book was completed. We make every attempt to produce our books on a timely basis, but the next revision of the specification is not introduced in time to make necessary changes.At the time of this writing, the HyperTransport I/O Link Specification Revision 1.04 is released. The 1.04 revision of the specification does not deal with the networking extensions but much of the work on the HyperTransport 1.05 and 1.1 revisions has been done by the HyperTransport Technical Working Group, and quite a bit of preliminary information on this important addition to the protocol has been released. Some of the more important additions to these specifications are summarized in this book. Please check the MindShare Web site (www.mindshare.com) for supplemental information, updates, and errata.Intended AudienceThis book is intended for use by hardware and software design and support personnel. The tutorial approach taken may also make it useful to technical personnel not directly involved design, verification, and other support functions.Prerequisite KnowledgeIt is recommended that the reader has a reasonable background in PC architecture, including experience or knowledge of an I/O bus and related protocol. The MindShare publication entitledISA System Architecturefocuses on various aspects of PCI architecture and provides the necessary background.Topics and OrganizationTopics covered in this book and the flow of the book are as follows:Part 1: Overview of HyperTransportChapter 1: Introduction to HyperTransportChapter 2: HT Architectural OverviewPart 2: HyperTransport Core TopicsChapter 3: Signal GroupsChapter 4: Packet ProtocolChapter 5: Flow ControlChapter 6: I/O OrderingChapter 7: Transaction ExamplesChapter 8: HT InterruptsChapter 9: System ManagementChapter 10: Error Detection and HandlingChapter 11: Routing PacketsChapter 12: Reset and InitializationChapter 13: Device ConfigurationChapter 14: ElectricalChapter 15: ClockingPart 3: HyperTransport Optional TopicsChapter 16: HyperTransport BridgesChapter 17: Double-Hosted ChainsChapter 18: HT Power ManagementChapter 19: Networking Extensions OverviewPart 4: HyperTransport Legacy SupportChapter 20: I/O CompatibilityChapter 21: Address RemappingChapter 22: x86 CPU CompatibilityAppendix A: Glossary of TermsIndexDocumentation ConventionsThis section defines the typographical convention used throughout this book.HyperTransportHyperTransport is a trademark of the HyperTransport Consortium. This book takes the liberty of abbreviating HyperTransport as "HT" to improve readability.Hexadecimal NotationAll hex numbers are followed by a lower case "h." For example:89F2BD02h0111hBinary NotationAll binary numbers are followed by a lower case "b." For example:1000 1001 1111 0010b01bDecimal NotationNumbers without any suffix are decimal. When required for clarity, decimal numbers are followed by a lower case "d." Examples:915512dByte Terminology and NotationThis book uses the following terminology regarding quantities of data:8-bits = 1 byte16-bits = 2 bytes, Word32-bits = 4 bytes, Double Word, Dword, or DW64-bits = 8 bytes, Quad Word, Qword, or QWBits Versus Bytes NotationThis book represents bit with lower case "b" and bytes with an upper case "B."For example:Megabits/second = Mb/sMegabytes/second = MB/sBit Fields and Groups of SignalsGroups of signals or bits are represented with the high-order bits first followed by the low-order bits and enclosed by brackets. For example:7:0Addr39:0CAD15:0Active Signal StatesSignals that are active low are followed by #, as in RESET#. Active high signalshave no suffix following the signal, as in PWROK.Visit Our Web SiteOur web site lists all of our courses and the delivery options available for each course:Self-paced DVDs and CDsLive web-delivered classesLive on-site classesAll of our books are listed and can be ordered in bound or e-book versionswww.mindshare.comWe Want Your FeedbackMindShare values your comments and suggestions. Contact us at:Phone: (719) 487-1417 or within the U.S. (800) 633-1440Fax: (719) 487-1434E-mail:don@mindshare.comorjay@mindshare.comFor information on MindShare seminars, DVDs, and books, check our Web siteor contactnancy@mindshare.comMailing Address:MindShare, Inc.4285 Slash Pine DriveColorado Springs, CO 809080321168453P02032003.